Computing systems are often coupled to a packet-based network. For example, Referring to FIG. 1, a computing system 100 may be coupled to an Ethernet network by a network interface 130. The computing system 100 may, for example have a central processing unit 105 internal bus 110, memory controller 115, and memory 120. In a network environment bursts of traffic 160 can arrive at any time, depending upon the actions of other client systems (not shown) coupled to the Ethernet network.
In some applications it is desirable to utilize computing system 100 as part of a “lossless” high speed (e.g., 1000 Mbit/s) network in which computing system 100 is designed to minimize data loss. That is, computing system 100 is designed and operated to avoid losing data packets in bursts of incoming traffic 160.
One problem with designing computing system 100 for “lossless” high-speed applications is that it limits the potential power-savings options that can be achieved in a cost-effective manner. Computing systems increasingly support a variety of power savings modes. However, power savings modes reflect a tradeoff between power consumption and performance. Typically, one tradeoff is a tradeoff between power consumption and system latency for performing memory accesses.
Many electronic systems have low power states, sometimes known as “sleep” states or “off states” although more generally there is now a spectrum of power down levels in addition to a “normal” operating state. For example, modern computer systems and graphics systems typically place different units and interfaces into a low power down state when specific units and interfaces are idle. As one example, a microprocessor may have power states C0-C3, where C0 is the operating state, C1 is a halt state, C2 is stop-clock state, and C3 is sleep state. Some microprocessors also have deep sleep (C4) and/or deeper sleep states that differ in how long it takes to wake up the processor. Some buses, such as the HyperTransport (HT) bus facilitate power management such that changes in processor state can signal changes to a lower power HT device state.
As examples of power down levels, a voltage of an integrated circuit, such as a central processing unit or memory controller, may be placed into low-voltage state as deeper power down level. As one example, some processors developed by the AMD corporation support a low power mode in which a CPU clock or voltage can be ramped down to save power. In these processors, an Alternate Voltage ID (AltVID) option permits chip voltage to be ramped down further after the clocks have ramped down. The AltVID option includes a programmable code sent to a voltage regulator to reduce microprocessor voltage to a minimum operational level for additional power savings. However, a tradeoff associated with using AltVID is that it has a higher transition latency than a conventional sleep mode.
In a network application bursts of data traffic 160 can arrive at the network interface at any time, even when computing system 100 is in power down level during an idle state. As a result, conventional computing systems designed to interface a network require a buffer 150 to store data that arrives as the computing system transitions out of a power-down level. That is, buffering is required for incoming data packets during the “wake up” time for all of the components along the upstream link to memory to transition to a normal operating level capable of receiving the incoming data. However, while the conventional approach works for low speed networks, in the context of high-speed networks (e.g., 1000 Mbits/s or greater) a prohibitive amount of buffering would be required to support a deep power down level while guaranteeing lossless behavior for bursts of traffic 160.
Therefore, it would be desirable to have an improved apparatus, system, and method for saving power in computing systems intended to be connected to a network in a lossless manner.